What You'll Do

Build predictive models for PPA & Timing:

Develop ML models to predict Power, Performance, Area, and timing violations critical paths, setup/hold slack at early RTL and synthesis stages to reduce costly signoff iterations.

Automate Physical Design:

Apply Reinforcement Learning RL and Graph Neural Networks GNNs to automate and optimize placement, routing, and floorplanning.

Process Chip Data at Scale:

Work directly with circuit netlist formats Verilog gate-level, LEF/DEF, SPEF, SDC, Liberty to build graph-based representations for ML consumption.

Deploy Closed-Loop ML:

Integrate trained ML models as closed-loop plugins within industry EDA tool scripts e.g., Tcl plugins so your predictions actively drive and influence real-time design decisions.

Predict Manufacturability:

Build DRC hotspot prediction models to catch lithography and design rule violations pre-tapeout.

Build Data Pipelines:

Architect pipelines to extract, label, and learn from massive simulation outputs generated by standard VLSI synthesis and physical design tools.

Collaborate Cross-Functionally:

Partner with RTL, physical design, and mixed-signal verification teams to identify bottlenecks and deploy your AI-assisted tooling into production flows.

What We're Looking For

Required:

Preferred:

Compensation & Benefits

Why Join Us