Build the next generation of ultra-low-power, brain-inspired compute systems powered by Wi-R.
Bengaluru, India (In Office)Full-time
About Ixana
Ixana is a Purdue University spinoff pioneering brain-inspired wearable computing. We've developed Wi-R, a patented communication tech that's 100x more energy-efficient than Bluetooth or Wi-Fi. Join our 60-person team building the next era of real-time, AI-powered human-computer interaction.
We provide comprehensive relocation support for engineers based outside Bengaluru.
The Wi-R Revolution
Wi-R is our patented non-radiative near-field communication technology that creates secure "wire-like wireless" experiences through small E-field bubbles around your body. This breakthrough enables unprecedented energy efficiency at sub-0.1 nanojoules per bit, making long-term wearable and implantable devices finally practical.
See Wi-R in Action: High-speed data, transferred through skin contact -
What You’ll Do
●Perform RTL integration of internal/external IPs and subsystems into top-level SoCs.
●Develop and maintain RTL wrappers, interconnect logic, and clock/reset infrastructures.
●Run lint, CDC, and early synthesis checks to ensure high-quality integration.
●Collaborate closely with design, verification, and physical design teams to ensure clean handoff.
●Debug simulation and synthesis issues at both block and chip levels.
●Maintain and automate integration flows using Python/Perl/Tcl.
●Contribute to design reviews and document integration flows.
What We're Looking For
Required:
●2-6 years of experience in RTL design and SoC/IP integration.
●Strong RTL skills using Verilog/SystemVerilog.
●Experience with AXI/AHB/APB protocols and interconnect architectures.
●Hands-on experience with tools like Synopsys Design Compiler, Spyglass, or similar.
●Proficiency in scripting languages Python, Perl, Tcl for flow automation.
●Understanding of synthesis, timing, and SoC assembly flows.
Preferred:
●Exposure to UPF/CPF and low-power design methodologies.
●Experience with SoC integration frameworks and custom EDA automation.
●Familiarity with high-performance, low-power compute architectures.